The present invention relates to a neuron computer realized by connecting an analog neuron chip through an analog time divisional transmission path and more particularly to an error absorbing system realized by using a weight correction, expanding the dynamic range of weight data expressed in the fixed decimal point method, and using a variable-width integration pulse.
In a conventional sequential processing computer (Neuman type) it is difficult to control a data process function in accordance with a variation in the usage method or environment. Therefore, an adaptive data processing method utilizing a parallel distribution system and a layered network is proposed. The back propagation method (D. E. Rumelhart, G. E. Hinton, and R. J. Williams, "Learning Internal Representations by Error Propagation", PARALLEL DISTRIBUTED PROCESSING, Vol.1, pp. 318-364, The MIT Press, 1986) receives particular attention because of its high practicality.
The back propagation method utilizes a layered structure network comprising a node called a basic unit and internal connection having weights. FIG. 1A shows the structure of a basic unit 1. Basic unit 1 carries out a process similar to a continuous neuron model. It comprises a multiple-input single-output system and further comprises a multiplication unit 2 for multiplying a plurality of inputs (Y.sub.h) by respective weights (W.sub.ih) of the internal connections, an accumulating unit 3 for adding all the multiplied results, and a threshold value processing unit 4 for outputting final output X.sub.i by applying a nonlinear threshold value process to the added values.
FIG. 1B shows a conceptual view of the structure of a layered neural network. Many basic units (1-h, 1-i, 1-j) are connected in layers as shown in FIG. 1B and the output signal patterns corresponding to the input signal patterns are output.
Upon learning, the weights (W.sub.ih) of connections between respective layers are determined in order to minimize the difference between the output patterns and a target teacher pattern. This learning is applied to a plurality of input patterns and then multiplexed. Upon an association operation, even if the input pattern contains information which is slightly incomplete upon the learning and therefore different from the complete information input upon the learning, the output pattern close to the teacher pattern provided upon learning is provided, thereby enabling a so-called associating process. To realize a neuron computer with such a structure, a transmission and reception of the data between basic units constituting a layered network is conducted by as small a number of wires as possible. This is a problem which should be solved when a complex data process is realized by forming multi-layers of the network structure and increasing the number of basic units.
However, the data process system explained above requires a large number of wires between the two layers, which prevents it from being made small when the system is formed into a chip. For example, consider a complete connection in which the number of adjacent layers is made the same and all the basic units 1 are connected to each other. In this case, the number of wires increases in proportion to the second power of the number of basic units, thereby resulting in a rapid increase in the number of wires. Further, its reliability cannot be increased when the data process system is manufactured into a chip, because the data process system includes an offset error and a gain error. If the data is expressed by a fixed decimal point method in which the decimal point exists next to the most significant bit, a number more than 1 cannot be expressed. Thus, the dynamic range of the data cannot be broadened.